This invention is directed to an electronic timepiece correction circuit and in particular to a correction circuit adapted to advance the count of a divider stage to be corrected without effecting an advance of the subsequent divider stages counting a lower frequency signal than the divider stage to be corrected. Although correction of each display digit in an electronic digital wristwatch is achieved by manually advancing the count of the divider stage providing timekeeping signals to the display digit to be corrected, such advancement causes the carry signal produced by the divider stage to be corrected to be advanced, thereby advancing the count of the next divider stage. For example, if the minute divider stage is advanced by one, the next divider stage, namely, the hours and date divider stages are advanced by a time period equal to the amount which the minute divider stage was advanced to. Thus, if the display reads 10:59:47 and it is desired to change the minute digit from 9 to 6, if the minute digit is advanced by seven to read 6, the 10 minute display, hour display and calendar display will be advanced by seven minutes, the time by which the minute display to be corrected is advanced. Nevertheless, since the actual time was 10:56:47, and the only incorrect digit was the minute digit, it is necessary to correct each of the subsequent divider stages which were advanced by the correction of the minutes digit, a condition which is less than completely satisfactory.